Current techniques of forming gate stack in the FinFET device structure starts with depositing high-k metal dielectric material such as HfO2, Al2O3, or La2O3 by ALD process. The process can be done either following the fin formation, referenced as the “gate first” scheme (also referenced as the metal inserted polysilicon), or it can be done after the formation of the source and drain in a process referred to as “gate last”, (also referenced as “replacement metal gate” (RMG) scheme). The gate first and gate last refer to whether a metal electrode is deposited before or after the high temperature activation anneals of the flow. It is then followed by a workfunction metal deposition to set the transistor threshold voltage. Typical materials that are employed include TiN, TiC, or TiAl.
Since the requirement for a threshold voltage between an n-type MOSFET transistor and p-type MOSFET differs, the gate stack formation can involve a certain patterning process, e.g., to deposit either one type of workfunction metal first on both n-type and p-type FETs, followed by removing it from one side, and then depositing the desired workfunction metal to set the right threshold voltage for both types of transistors. The next step consists in depositing the gate contact material to lower the gate resistance. In the gate first scheme, the process is followed by an offset space deposition, and an epitaxial process to form the source and drain of the transistors. While in the gate last (RMG) scheme, the process is followed by the middle-of-the-line (MOL) source/drain contact formation such as by a contact etch, TiN barrier layer and W film deposition.
As the device continues to the nanometer scaling, the requirement for the transistor drive current performance becomes increasingly more difficult to meet. One difficulty that encountered resides in the conventional stress effect, such as an embedded silicon germanium, embedded silicon carbon source drain, and dual stress silicon nitride liner set to boost the carrier mobility that diminishes significantly with the scaling of the gate contact pitch.
The process typically starts with the recess of a silicon source and the drain region, followed by a SiGe or SiC film epitaxial growth in the trench region. Typically, it consists of three different layers, the first layer referenced as the buffer layer which is usually lightly doped to provide the junction gradient control and device short channel electrostatic benefit. Then, the process continues with the main layer heavily doped to lower the source and drain sheet resistance. A typical dopant is boron for a p-type MOSFET, and phosphorus or arsenic for the n-type transistor. The incorporation of the germanium for a p-type MOSFET and carbon for the n-type MOSFET is by introducing the strain from the source and drain region to the channel region. The fact that germanium atom has a larger lattice constant than silicon atom produces a tensile strain in the SiGe film itself when it creates bonding with the silicon atom. The stress is then transferred to the channel region to generate a compressive strain that is favorable for the transport of holes and thus enhances the p-type MOSFET drive current. The effect of the carbon atom is just the opposite. The fact that carbon atom has a smaller lattice constant than silicon atom produces a compressive strain in the SiC film itself when it creates bonding with the silicon atom. The stress is then transferred to the channel region to generate the tensile strain that is favorable for the transport of electrons and thus enhances the n-type MOSFET drive current. The stress effect from the embedded source drain either is made of SiGe or SiC that drops significantly when the device gate pitch continues to scale. The pitch scaling is necessary because of the chip area reduction set to improve the cost structure of the semiconductor. However, because of the pitch scaling, the available space for the source and drain stressor formation becoming smaller and smaller, this leading to the decrease of the stressor volume and a greatly reduction of the stress effect from the source and the drain region. The stress effect has been estimated to be about only 20-30% left when the technology feature size shrinks from the 22 nm node technology to the 14 nm node technology.
Another factor that limits the usage of source and drain extrinsic stressor is the transition from the planar device structure to the FinFFT type of the transistor structure. The fact that FinFET device is provided of a thin slab of silicon as the channel (typical dimensions are 10 nm width and 30 nm tall) which signifies that the area for stress coupling is much reduced compared to the planar device structure which makes the stress coupling efficiency, defined as the ratio between stress level in the source and drain region to the stress level in the device channel region that becomes significantly less compared to the planar device. The reduction of the aforementioned two effects (stressor volume and stress coupling) makes the stress engineering of the FinFET device structure ever more challenging compared to that of previous generations.
The challenge for the gate induced strain, however, is how to implement it through the selection of gate stack materials to meet not only the channel strain requirement for carrier mobility boost, but also a workfunction setting to meet the transistor threshold voltage requirement. It further has to have minimized gate stack inversion thickness impact so that the transistor drive current benefit from gate induced strain will not be compromised. Gate stack materials such as TiN, TaN, and TiC have a certain level of strain itself, preferably in the range of 2 GPa to 3 GPa which is quite significant in terms of producing channel strain when the coupling ratio is sufficiently high. The contact material such as W is also known for having a tensile strain favorable for the transistor mobility enhancement.
The challenge is, as previously mentioned, how to design the gate stack thickness and structure such that the stress benefit can be maximized, but at the same time, without affecting other device parametrics, such as the transistor threshold voltage and the inversion gate stack thickness.